Note that there is a specified minimum enclosure in the design rules for vias between polysilicon and metal. A wire automatically helps with choosing layer, and may also be used to create vias to another layer by left-clicking.Ī complete layout could look something like this: To create a connection between to nodes you can either create a wire (Ctrl+W) or a path (P). NWell) choose the wanted layer on the left side then press R. DRD Enforce On prevents you from doing anything that breaks the rules, and DRD Notify tells you if what you are doing is illegal. if we want to stretch a part.ĭRD stands for Dynamic Design Rule Checking and are helpful while laying out your design. Partial Select means that we are able to select individual pieces of a device, e.g. However, you can use Ctrl++ (that is Ctrl and +-key ) to turn on or off the nets for the selected device.į4 switches between Full and Partial Select. This will give you a all the nets that are uncompleted and can be very daunting. This is accomplished with Connectivity -> Nets -> Show/Hide All Incomplete Nets. To help you place the the devices correctly it is helpful to see which devices that connect to each other and how. This, however, will probably not give you the desired result. If you are extremely lazy you can autoplace the components with Place -> Custom Digital -> Placer. Remember that the positions may be tweaked later. This is very helpful to line up our design. This opens a windows that lets us define the position of our pins. Notice how the ntap1 is highlighted in the schematic when clicked in the layout window. The purple box is the PR boundary in which are layout must be contained. Remember to uncheck Create under the sub!-pin since this is not needed.Ĭhange the Label options to a smaller font size (about 0.1 is ok). We also want two gnd-pins which also can be defined here. This means that they will intersect each other and must be in different layers. We want the gnd and bit-lines to be vertical, and vdd and word-lines to be horizontal. For our cell we need to change the IO-pins. In this window we define which of our devices we want to place, the I/O pins, PR boundary (the area which our cell must be within) and floorplan settings (if needed). To place all the devices from the schematic press Connectivity -> Generate -> All From Source. You should, however, dissect them to understand how they work. for different sized, so it is not needed to draw these from scratch. IHP has already defined transistors, pins, etc. This defines the the distance before snapping to another object etc. Set gravity on(you can turn this off later with the g-key if you dont like it), and aperture around 0.1. Now press Shift-E to open the Layout Editor Options. Set the X and Y Snap Spacing to reflect the grid rules. Remember that all size-values are in micrometers. In Layout XL press E to open the Display Options-window. In the Layout Rules-document we read what our drawing-grid restrictions are (bottom of page 10). This is very useful as when we add our devices in the layout we can see which device they represent in the schematic as they get highlighted.īefore anything you must define some options to avoid a lot of DRC-errors down the line. Layout XL opens with a new black empty canvas. from "sram" to "sram-fixed").įrom the schematic click Launch -> Layout XL to open the layout environment. If you do not want to change your schematic, make a copy to another cell (e.g. This makes it easier to produce the right transistor-sizes etc. If you're laying out just one cell (in our case a SRAM-cell) make sure it contains defined values and not just pPar("")-values. Other documents are found in "eda/design_kits/ihp_sg13/SG13S_618_rev1.12.0/doc/html/" Also make sure you understand the Layout Rules document. Especially the part of connecting the substrate (chapter 8.2) and layout (chapter 9). It can be found on the SG13SFeatures tab on the Virtuoso console window, or in the folder "/eda/design_kits/ihp_sg13/SG13S_618_rev1.12.0/doc/pdf/" on the mikroserver.
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